A silicon epitaxial wafer is manufactured, for example, in the following manner.
First, a silicon single crystal wafer is placed in a reaction chamber of a vapor phase epitaxy apparatus. The interior of the reaction chamber is then heated to temperatures from 1100° C. to 1200° C. while a hydrogen gas flows.
Next, a native oxide film (SiO2: Silicon Dioxide) formed on the surface of the wafer is removed after the temperature of the interior of the reaction chamber reaches 1100° C.
In this condition, a silicon raw material gas such as trichlorosilane (SiHCl3) and a dopant gas such as diborane (B2H6) and phosphine (PH3) are supplied to the interior of the reaction chamber together with a hydrogen gas. A silicon single crystal thin film is grown by the vapor phase epitaxy on the surface of the wafer in this manner.
After growing the thin film, the supply of the raw material gas and dopant gas is stopped, and the reaction chamber is cooled while the wafer is held in a hydrogen atmosphere.
For conventional silicon epitaxial wafers, {100} substrates having a {100} plane as a main plane are mainly used as the substrates on which the silicon single crystal thin film is to be grown by the vapor phase epitaxy.
On the other hand, substrates having a {110} plane as a main plane have a characteristic of higher electron hole mobility than that of the {100} substrates, thereby enabling a faster CMOS. In recent years, the {110} substrates have therefore drawn attention.
The {110} substrate, however, has a problem in that surface quality, such as Haze and surface roughness, greatly deteriorates when a silicon homoepitaxial layer is grown on its surface in comparison with the {100} substrate.
In regard to this problem, studies are being conducted to improve the surface quality, such as Haze and surface roughness, of a silicon epitaxial wafer using the {110} substrate. For example, a method of using a silicon wafer having a plane that is slightly tilted in a <100>, <110>, or <111> direction from the {110} plane to improve the surface quality of the silicon homoepitaxial layer has been known (See Patent Documents 1 and 2).